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Known Design Marginality/Exceptions to Functional Specifications
Advisory NMI: Writing a " 0" to Any of the CNMIFRC/MNMIFRC Register Bits Clears the
Corresponding Flag Bit in CNMIFLG/MNMIFLG
Revision(s) Affected 0
Details Writing a "0" to any of the bits in the Control Subsystem CNMIFRC register clears the
corresponding bits in the CNMIFLG register. Likewise, writing a "0" to any of the bits in
the Master Subsystem MNMIFRC register clears the corresponding bits in the MNMIFLG
register.
Workaround(s) Do not write "0" to any of the bits in the CNMIFRC register or MNMIFRC register. To
clear the CNMIFLG and MNMIFLG bits, write a "1" to the corresponding bits in the
respective CNMIFLGCLR and MNMIFLGCLR registers.
This will be fixed in the next revision of the silicon.
Advisory PLL: Setting SYSPLLMULT or UPLLMULT to 0x0000 causes " /0" Condition in PLL
Logic
Revision(s) Affected 0
Details Setting the SYSPLLMULT register or UPLLMULT register to 0x0000 to bypass the PLL
causes a "/0" condition in the PLL logic and results in an unstable PLL output clock.
Workaround(s) Do not write 0x0000 to the SYSPLLMULT register or UPLLMULT register to bypass
either PLLs. Instead, to bypass the system PLL, set SYSPLLCTL[SPLLCLKEN] = 0. To
bypass the USB PLL, set UPLLCTL[UPLLCLKEN] = 0.
This will be fixed in the next revision of the silicon.
Advisory USB: VBUS Pin May Clamp to 3.3-V Supply, Preventing Proper OTG Mode
Operation
Revision(s) Affected 0
Details The VBUS pin may clamp to V
DDIO
, preventing the pulldown resistors from taking effect in
USB-OTG mode when attempting to end a session.
Workaround(s) None
Advisory USB: Host Mode — Cannot Communicate With Low-Speed Device Through a Hub
Revision(s) Affected 0
Details When the USB controller is operating as a Host and a low-speed packet is sent to a
device through a hub, the subsequent Start-of-Frame is corrupted. After a period of time,
this corruption causes the USB controller to lose synchronization with the hub, which
results in data corruption.
Workaround(s) None
9
SPRZ357B– August 2011– Revised January 2012 F28M35x Concerto MCU Silicon Errata
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