MAP electronics Cocerto-B Especificaciones descargar pdf (Pagina 17)

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Usage Notes and Known Design Exceptions to Functional Specifications

Advisory UART: RTRIS Bit in the UARTRIS Register is Only Set When the Interrupt is

Enabled

Revision(s) Affected 0, A, B

Details The RTRIS (UART Receive Time-Out Raw Interrupt Status) bit in the UART Raw

Interrupt Status (UARTRIS) register should be set when a receive time-out occurs,

regardless of the state of the RTIM enable bit in the UART Interrupt Mask (UARTIM)

when a receive time-out occurs.

Workaround(s) For applications that require polled operation, the RTIM bit can be set while the UART

interrupt is disabled in the NVIC using the IntDisable(n) function in the StellarisWare

Peripheral Driver Library, where n is 21, 22, or 49, depending on whether UART0,

UART1, or UART2 is used. With this configuration, software can poll the RTRIS bit, but

the interrupt is not reported to the NVIC.

Advisory VREG: VREG 'Warn Lo/High' Feature Does Not Work as Intended

Revision(s) Affected 0, A, B

Details The VREG "Warn Lo/High" feature should not be used or enabled in the device. Do not

set the VREGWARNE bit in the MNMICFG register as it could negatively affect the

VREG output voltage.

Workaround(s) None

Advisory System Control: Clock Configuration Should Not be Changed When There are

Pending or On-going Accesses to Shared RAM (Cx and Sx) or to Analog

Subsystem

Revision(s) Affected 0, A, B

Details If the clock configuration is being changed (for example, changing the clock divider for

Cortex-M3) when there is a pending or on-going access to Shared RAM (Cx/Sx) or to

the Analog Subsystem, the access could generate an error.

Workaround(s) Software should ensure that there is no pending or on-going access to Shared RAM or

to the Analog Subsystem when the clock configuration is being changed.

Advisory ePWM: ePWM7 is Clocked by CPUCLK and Will Stop During IDLE

Revision(s) Affected 0, A, B

Details The ePWM7 is clocked by C28x CPUCLK. When the CPUCLK stops, ePWM7 will also

stop. The C28x (and ePWM7) will stop during:

• C28x low-power IDLE mode

• C28x debugger halt

Other ePWM modules are clocked by SYSCLK, which does not stop during IDLE or

debugger halt.

Workaround(s) None. Use other ePWM modules if the IDLE mode is used or ePWM must remain active

during debugger HALT.

SPRZ357J–August 2011–Revised July 2014 F28M35x Concerto™ MCU Silicon Errata

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MAP electronics Cocerto-B Especificaciones Pagina 17