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Usage Notes and Known Design Exceptions to Functional Specifications

Advisory RAM Controller: Cortex-M3 Correctable Error Address Register Always has Value

0x0

Revision(s) Affected 0, A, B

Details The Correctable Error Address Register should capture the address for which the

correctable error (1-bit ECC error) occurred, but the Correctable Error Address Register

mapped to the Cortex-M3 core will always have value 0x0.

Workaround(s) None. The original intent of this register is to aid in debugging. Note that correctable

errors do get corrected, so this erratum does not affect device functionality.

Advisory RAM Controller: C28x Correctable Error Address Register Always has Value 0x0

Revision(s) Affected 0

Details The Correctable Error Address Register should capture the address for which the

correctable error (1-bit ECC error) occurred, but the Correctable Error Address Register

mapped to the C28x core will always have value 0x0.

Workaround(s) None. The original intent of this register is to aid in debugging. Note that correctable

errors do get corrected, so this erratum does not affect device functionality.

Advisory RAM Controller: Cortex-M3 Accesses to Shared RAM (Cx and Sx) and to MSG

RAM Do Not Work When Any Other Master (µDMA/C28x/DMA) Simultaneously

Accesses the Same Memory

Revision(s) Affected 0

Details If Cortex-M3 accesses Shared RAM (Cx and Sx) or MSG RAM when any other master

(µDMA/C28x/DMA) accesses the same memory, data and parity may get corrupted in

the memory.

Workaround(s) When Cortex-M3 accesses Shared RAM or MSG RAM, no other master

(µDMA/C28x/DMA) should access the same memory at that time.

This is fixed in Revision A silicon.

Advisory RAM Controller: µDMA Accesses to Shared RAM (Cx and Sx) and to MSG RAM Do

Not Work When Any Other Master (Cortex-M3/C28x/DMA) Simultaneously

Accesses the Same Memory

Revision(s) Affected 0

Details If µDMA accesses Shared RAM (Cx and Sx) or MSG RAM when any other master

(Cortex-M3/C28x/DMA) accesses the same memory, data and parity may get corrupted

in the memory.

Workaround(s) When µDMA accesses Shared RAM or MSG RAM, no other master (Cortex-

M3/C28x/DMA) should access the same memory at that time.

This is fixed in Revision A silicon.

SPRZ357J–August 2011–Revised July 2014 F28M35x Concerto™ MCU Silicon Errata

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MAP electronics Cocerto-B Especificaciones Pagina 21