MAP electronics Cocerto-B Especificaciones descargar pdf (Pagina 30)

Usage Notes and Known Design Exceptions to Functional Specifications

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Advisory NMI: Writing a "0" to Any of the CNMIFRC or MNMIFRC Register Bits Clears the

Corresponding Flag Bit in CNMIFLG or MNMIFLG

Revision(s) Affected 0

Details Writing a "0" to any of the bits in the Control Subsystem CNMIFRC register clears the

corresponding bits in the CNMIFLG register. Likewise, writing a "0" to any of the bits in

the Master Subsystem MNMIFRC register clears the corresponding bits in the MNMIFLG

Workaround(s) Do not write "0" to any of the bits in the CNMIFRC register or MNMIFRC register. To

clear the CNMIFLG and MNMIFLG bits, write a "1" to the corresponding bits in the

respective CNMIFLGCLR and MNMIFLGCLR registers.

This is fixed in Revision A silicon.

Advisory PLL: Setting SYSPLLMULT or UPLLMULT to 0x0000 causes "/0" Condition in PLL

Logic

Revision(s) Affected 0

Details Setting the SYSPLLMULT register or UPLLMULT register to 0x0000 to bypass the PLL

causes a "/0" condition in the PLL logic and results in an unstable PLL output clock.

Workaround(s) Do not write 0x0000 to the SYSPLLMULT register or UPLLMULT register to bypass

either PLLs. Instead, to bypass the system PLL, set SYSPLLCTL[SPLLCLKEN] = 0. To

bypass the USB PLL, set UPLLCTL[UPLLCLKEN] = 0.

This is fixed in Revision A silicon.

F28M35x Concerto™ MCU Silicon Errata SPRZ357J–August 2011–Revised July 2014

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MAP electronics Cocerto-B Especificaciones Pagina 30